A programmable counter/timer based on HDL (Hardware Description Language) design is proposed. The Intel 8254 is selected for defining the functionality and specifications of the programmable counter/timer. VHDL programs are first eveloped to emulate the functional operation of 8254. Next, the programs are verified by simulation using ModelSim. Then the hardware circuit is synthesized and analyzed. The experimental results show that, based on the proposed VHDL-driven design, a high complexity programmable counter/timer can be realized by programmable logic quickly and cost-effectively.
