Design of Programmable Counter/Timer Using VHDL

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Title:	Design of Programmable Counter/Timer Using VHDL
Authors:	許宏任黃建豪賴茂富
Contributors:	工學院
Keywords:	VHDL 可程式計數器／計時器 VHDL FPGA COUNTER/TIMER
Date:	2002-06-01
Issue Date:	2012-05-09 15:12:25 (UTC+8)
Abstract:	本論文提出以HDL（硬體描述語言）爲基礎的設計方式來實現司程式計數器／計時器。選擇英特爾8254晶片作爲定義該可程式計數器／計時器的功能和規格。VHDL首次用來作爲發展8254的工具，並藉由使用Model Sim來驗證其功能的正確性。再透過合成其硬體電路加以分析。基於本文所提出以VHDL爲基礎的設計方式，可從實驗結果顯示，具有高複雜度的可程式計數器／計時器可以快速且符合成本效益的加以實現。 A programmable counter/timer based on HDL (Hardware Description Language) design is proposed. The Intel 8254 is selected for defining the functionality and specifications of the programmable counter/timer. VHDL programs are first eveloped to emulate the functional operation of 8254. Next, the programs are verified by simulation using ModelSim. Then the hardware circuit is synthesized and analyzed. The experimental results show that, based on the proposed VHDL-driven design, a high complexity programmable counter/timer can be realized by programmable logic quickly and cost-effectively.
Relation:	華岡工程學報 16期 p.111 -145
Appears in Collections:	[College of Engineering] Chinese Culture University Hwa Kang Journal of Engineering

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