Characteristics of Lock-in Thermography Signal from Solder Bump Cracking in Wafer-level Chip Scale Packaging for Internet of Things Applications

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Title:	Characteristics of Lock-in Thermography Signal from Solder Bump Cracking in Wafer-level Chip Scale Packaging for Internet of Things Applications
Authors:	Wu, IC (Wu, I-Chih) Huang, YJ (Huang, Yu-Jung) Wang, MH (Wang, Min-Haw) Jang, LS (Jang, Ling-Sheng)
Contributors:	電機工程系
Keywords:	DEVICES SENSOR
Date:	2018
Issue Date:	2019-01-22 11:11:57 (UTC+8)
Abstract:	Internet of Things (IoT) devices are increasingly incorporating miniature multilayered integrated architectures. However, the localization of faults in the interconnection of solder bumps remains challenging. The problem of solder bump cracking (SBC), which causes failure of interconnections subjected to evaluation of board-level reliability (BLR) in wafer-level chip scale packaging (WLCSP) for IoT applications, is studied. Lock-in thermography (LIT) monitoring is a promising method for failure analysis (FA) of SBC. This method makes use of indium-antimonide (InSb) as the infrared (IR) sensor. In this study, we characterized the drop test behavior of WLCSP and the critical units located at the printed circuit board (PCB) center. LIT is shown to enable the detection of the fault location between the IoT chip and PCB in complex daisy chain interconnections, and more accurate detection as a result of applying LIT to thermal imaging for the resistive openings of SBC is discussed. The experimental results show that the employment of LIT enhances the visibility of the resistive openings. The analysis method can also be extended to shorts or leakage currents in thermally active failures, especially in packaged semiconductors.
Appears in Collections:	[Department of Electrical Engineering ] journal articles

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