VLSI Architecture Design of a High Performance Clustering Analyzer

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Title:	VLSI Architecture Design of a High Performance Clustering Analyzer 高效能聚類分析之架構設計
Other Titles:	串列輸入聚類分析之VLSI架構
Authors:	賴茂富
Contributors:	華岡工程學報
Keywords:	聚類分析平行處理
Date:	1997-06
Issue Date:	2014-11-04 13:58:56 (UTC+8)
Abstract:	聚類分析通常使用在影像處理與標形辨識，本文提出一種新的VLSI架構，以提高聚類分析處理速度，並大量減少電路之複雜度，故利用此種新的方法，可以實現高效能聚類分析之VLSI設計。 Clustering analysis is an important technique in image processing and pattern recognition. The squared-error clustering algorithm is the most well-known method in clustering analysis Recent progress in VLSI technology stimulates the idea to implement the squared-error clustering algorithm by hardware for high speed application. This paper presents a high performance VLSI architecture for the squared-error clustering algorithm. The architecture can reduces the huge number of processing elements which are required by other architectures. In addition, the time complexity of our architecture is lower than other architectures. The VLSI implementation for high performance clustering analyzers can be realized with considerately less circuit complexity based on this novel architecture.
Relation:	華岡工程學報； 11 期 (1997 / 06 / 01) ， P23 - 32
Appears in Collections:	[College of Engineering] Chinese Culture University Hwa Kang Journal of Engineering

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