Area-Delay Efficient Digit-Serial Multiplier Based on k-Partitioning Scheme Combined With TMVP Block Recombination Approach

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Title:	Area-Delay Efficient Digit-Serial Multiplier Based on k-Partitioning Scheme Combined With TMVP Block Recombination Approach
Authors:	Lee, CY (Lee, Chiou-Yng) Meher, PK (Meher, Pramod Kumar) Liu, CH (Liu, Chung-Hsin)
Contributors:	資工系
Keywords:	Block recombination digit-serial multiplication Karatsuba algorithm (KA) shifted polynomial basis (SPB) subquadratic space complexity
Date:	2016-07
Issue Date:	2017-04-13 09:25:46 (UTC+8)
Abstract:	Shifted polynomial basis (SPB) and generalized polynomial basis (GPB) are two efficient bases of representation in binary extension fields, and are widely studied. In this paper, we use the GPB formulation to derive a new modified SPB (MSPB) representation for arbitrary irreducible trinomials and pentanomials. It is shown that the basis conversion from the MSPB to the SPB for trinomials is free of hardware cost. We have shown that multiplication based on SPB and MSPB representations can make use of Toeplitz matrix-vector product (TMVP) formulation. The existing TMVP block recombination (TMVPBR) approach is used here to derive an efficient k-partitioning TMVPBR decomposition for digit-serial double basis multiplication that can achieve subquadratic space complexity. From synthesis results, we have shown that the proposed multiplier has less area and less area-delay product compared with the existing digit-serial multipliers. We also show that the proposed multiplier using k-partitioning TMVPBR decomposition can provide a better tradeoff between time and space complexities.
Relation:	IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 卷: 24期: 7 頁碼: 2413-2425
Appears in Collections:	[Department of Computer Science and Information Engineering] journal articles

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