適用於嵌入式硬體平臺之色彩空間轉換器設計

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Title:	適用於嵌入式硬體平臺之色彩空間轉換器設計 A Cost-Efficient VLSI Architecture for Color Space Conversion Processors
Authors:	夏至賢孔燕張智貞
Contributors:	圖書館
Keywords:	影像色彩處理器色彩空間轉換管線架構摺疊架構 Image color processor Color space conversion Pipeline architecture Folded architecture
Date:	2016-11
Issue Date:	2017-03-24 14:48:43 (UTC+8)
Abstract:	般在設計色彩空間轉換器(Color Space Conversion, CSC)時，因為RGB 三原色的關係在超大型積體電路(Very Large Scale Integration, VLSI)設計時會使用較多的暫存器(Register)進而產生其硬體成本的增加。有鑑於此，本研究提出了一個管線架構(Pipelining architecture)並配合摺疊架構(Folding architecture)的設計，應用於RGB 轉換至YCbCr 色彩空間；在改良架構中以管線處理的步驟，將其處理優化，並利用三原色非同步處理的特性配合摺疊架構成一組管線架構，使其具有即時性、高硬體使用率、以及低成本的特性。最後，本文使用Xilinx FPGA 實現，將實際的 RGB 資料經由本系統做轉換並處理後的YCbCr 值與其理論值比較，得到較低的誤差平均值為 Y=0.231%、Cb=0.221%、Cr=0.149%、減少暫存器使用量為36.59%以及減少邏輯元件的使用量為 67.57%。 During general Color Space Conversion (CSC), the Red, Green, and Blue (RGB) color model in VLSI requires many registers and thus is associated with high hardware-related costs. This study proposed a folded and pipeline architectures in which RGB was converted into a YCbCr color space. The new design included optimized pipeline processing and independent processing of RGB channels and had higher instantaneity, hardware usage, and cost-efficiency. Finally, Xilinx FPGA was used to compare the actual RGB data and the converted and processed YCbCr values and theoretical values. The errors obtained were minimized to Y= 0.231%, Cb= 0.221%, and Cr= 0.149% and register usage and logical element usage were decreased to 36.59% and 67.57%, respectively.
Relation:	中正嶺學報 45:2(A) 2016.11[民105.11] 頁133-142
Appears in Collections:	[Department of Electrical Engineering ] journal articles

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