文化大學機構典藏 CCUR:Item 987654321/30576
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    Please use this identifier to cite or link to this item: https://irlib.pccu.edu.tw/handle/987654321/30576


    Title: Efficient Digit-Serial KA-Based Multiplier Over Binary Extension Fields Using Block Recombination Approach
    Authors: Liu, Chung-Hsin
    Lee, Chiou-Yng
    Meher, Pramod Kumar
    Contributors: Dept Comp Sci & Informat Engn
    Keywords: Block recombination architecture
    digit-serial multiplication
    finite field
    Karatsuba algorithm
    Date: 2015-08
    Issue Date: 2015-10-20 15:52:44 (UTC+8)
    Abstract: It is well-known that the (a, b)-way Karatsuba algorithm (KA) with a not equal b is used for efficient digit-serial multiplication with subquadratic space complexity architecture. In this paper, based on (a, b)-way KA decomposition, we have derived a novel kappa-way block recombination KA (BRKA) decomposition for digit-serial multiplication. The proposed kappa-way BRKA is formed by a power of 2 polynomial decomposition. By theoretical analysis, it is shown that kappa-way BRKA can provide the necessary tradeoff between space and time complexity. Using (4,2)-way KA to construct the proposed kappa-way BRKA architecture in GF(2(409)), it is shown that the proposed 2-way BRKA approach requires less area, and the proposed 8-way BRKA approach requires less computation time and less area-time product compared to compared the existing (a, b)-way KA decomposition.
    Relation: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 卷: 62 期: 8 頁碼: 2044-2051
    Appears in Collections:[Department of Computer Science and Information Engineering] journal articles

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