使用ITA演算法和休眠檢測模擬MOSFET加上連接線之大型電路

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Title:	使用ITA演算法和休眠檢測模擬MOSFET加上連接線之大型電路 Large-scale Circuit Simulation for MOSFET Circuits with Interconnects Using Iterated Timing Analysis and Latency-checking Method
Authors:	陳俊榮昌隆孫振東李志仁張耀鴻周立平楊泰寧
Contributors:	華岡工程學報
Keywords:	電路模擬傳輸線基於鬆弛 ITA演算法休眠 circuit simulation transmission lines relaxation-based ITA algorithm latency
Date:	2011-01
Issue Date:	2014-10-31 14:28:40 (UTC+8)
Abstract:	此篇論文討論了使用Iterated Timing Analysis演算法（ITA Algorithm）進行現代電路設計界常遇到的大型MOSFET和有損交連傳輸線電路之模擬，其中ITA扮演主要演算法的角色，一個全時域的的傳輸線計算法則扮演連接線模擬器的角色，這兩種數值演算法都利用了電路的休眠（latency）特性進行加速，所發表方法均加以實做並透過真實的電路模擬驗證，所呈現計算效能的進步相當明顯而成功。此篇論文的結果說明了一個可行的處理大型內含許多連接線之MOSFET電路的模擬法，對於實際應用有相當的貢獻。 In this paper, we propose methods to perform large-scale circuit simulation for MOSFET circuits containing lossy coupled transmission lines that have been encountered in modern circuit design community. We utilize the fast multi-rate ITA (Iterated Timing Analysis) algorithm and a full time-domain transmission line calculation algorithm based on the Method of Characteristic. Various methods to speedup the transmission line calculation algorithm have been presented. All proposed methods have been implemented and tested to justify their superior performance.
Relation:	華岡工程學報； 27 期 (2011 / 01 / 01) ， P125 - 131
Appears in Collections:	[College of Engineering] Chinese Culture University Hwa Kang Journal of Engineering

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