鈦酸鋇奈米顆粒嵌鑲於多項奈米線材結構之場效電晶體研究

文化大學機構典藏 CCUR > 理工學院 > 工學院 > 化學工程與材料工程學系暨碩士班 > 研究計畫 > Item 987654321/26905

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題名:	鈦酸鋇奈米顆粒嵌鑲於多項奈米線材結構之場效電晶體研究 Studies on the Field Effect Transistors by Embedding Barium Titanate Nanoparticles into Various Nanowires
作者:	施漢章
貢獻者:	化學工程與材料工程學系奈米材料碩士班
日期:	2013-08
上傳時間:	2014-03-03 09:51:50 (UTC+8)
摘要:	在過去幾十年中，整合化元件因為微電子在基礎物理和成本上的限制，進而停滯不前。所幸近代的奈米科技，自組裝技術已有大幅進步。由下而上的自組裝奈米材料，能藉由粒子間之作用力互相聚集排列形成特定的結構，例如像是分子、量子點及奈米線，就能藉由控制材料的尺寸、結構和化學組成去克服傳統微電子技術的極限。至今，很多電子元件都以一維奈米晶體當作基底表現出獨特的功能。如氧化鋅(ZnO)奈米線，其場效電晶體就因具有調變通道傳導的能力，經表面工程處理，達到調變臨界電壓的能力。鐵電場效電晶體，因能夠提供非破壞性讀出記憶、低功耗、良好記憶時間和快速反應速度。這些特性讓非揮發性記憶體能廣泛使用在便攜式電子元件上，其記憶功能源自於藉由切換極化的鐵電電子去誘使電荷在半導體通道中，進而調變通道的傳導能力。因此吾人規劃一個一年的專題研究計畫，主要是針對單一奈米線及鐵電奈米顆粒組裝及應用之非揮發性記憶元件及邏輯電路，分敘如下： 1. 前半年度：先合成各式奈米線(氧化鋅、氮化鎵、氧化鎵、氧化錫、和矽)，後去附著有鐵電特性的鈦酸鋇奈米顆粒，進而在大比表面積的材料上去控制通道的傳導性。 2. 後半年度：設計所合成出的各式奈米線，在元件和電路的圖樣伴隨著光對準、曝光和光阻剝離的半導體製作程序，使這些元件能達到非揮發性記憶體的要求。 In the past decade, the integrated devices technology was not enhanced sharply due to the limitations of the conventional microelectronic technology. Thanks to the modern physics, the technology of bottom-up self-assembly would be able to improve this limitation. In the process of self-assembly, the unique nanostructures and patterns can be made by the interactions between atomics. As well as, the sizes, architectures and chemical compositions in many materials’ species, such as molecules, quantum and nanowires, can be controlled by the self-assembly process. Therefore, self-assembly process would be the best way to overcome the limitations of the conventional microelectronic technology. The well-defined nanodevices based on one dimension nanocrystals demonstrate a perfect performance in the future applications. For instance, the field-effect transistors (FETs) based on the nanowires of ZnO, GaN, Ga2O3, SnO2 and Si are the potential candidates in applications of memory devices and combinations of logical circuits, because of their controllable channel conductivities. On the other hand, it is amazing that the FETs based on one dimension nanowires of ZnO, GaN, Ga2O3, SnO2 and Si obtain the controllable abilities of threshold voltages via the surface engineering of an individual nanowire. Ferroelectric (FE) FETs have attracted a great deal of attention due to their nondestructive memory readout, low power consumption, good retention, and fast response time, which have been widely used as promising nonvolatile memory components for portable electronic devices such as digital cameras, mobile phones, and smart debit cards. The memory function of (FE) FETs is derived from the modulation of the channel conductance by switching the polarization of the FE electrically, which induces charges in a semiconducting channel. Therefore, the end target of this one-year project is to manufacture a stable nanowire and FE nanoparticles in order to enhance the channel conductance and to accelerate the response time of the nonvolatile memory devices and logic circuits. In the first six months, various nanowires (e.g. ZnO, GaN, Ga2O3, SnO2, and Si) will be fabricated to cohere FE BaTiO3 nanoparticles in order to control the channel conductance under the large surface to volume ratio. In the last six months, patterns of memory devices and logic circuits will be designed and applied by fabricating nanowires with photo-alignment, exposure and photoresist developing. The devices demonstrate high on/off ratio, fast response time, and a long retention time, which highly improve the performance for applications in nonvolatile memory.
顯示於類別:	[化學工程與材料工程學系暨碩士班] 研究計畫

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