利用3D模擬與製程技術製作最佳的氮化金屬與High-k閘極結構用於 CMOS 次 10奈米

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題名:	利用3D模擬與製程技術製作最佳的氮化金屬與High-k閘極結構用於 CMOS 次 10奈米 Robust Metal Nitride with High-K Gate Stack by 3d Simulation and Integration for Cmos Sub 10 Nm
作者:	譚湘瑜
貢獻者:	電機工程學系
關鍵詞:	金屬閘極高介電係數材料 TiN TaN 金屬氮化物
日期:	2012~2013
上傳時間:	2013-03-04 15:06:12 (UTC+8)
摘要:	利用3D模擬與製程技術製作最佳的氮化金屬與High-k閘極結構用於 CMOS 次 10奈米現今的先進的閘極氧化層的評估正式進入未來的28 奈米和10 奈米階段。邏輯電路技術正處於一個材料革命。鉿為主的高介電常數介電材料已開始取代氧化矽或氮氧化矽閘極絕緣層，金屬氧化物半導體場效應晶體管（MOSFET）和金屬取代多晶矽電閘極。因此，金屬閘極（MG）/高電介質（HK）/矽閘極結構是勢在必行。金屬氮化物被視為潛在候選材料主要是間隙中的電極由於其較高的熱穩定性，與傳統的CMOS 技術的兼容性。採用金屬閘極，在傳統的CMOS 技術，構成新的挑戰。據報導，金屬氮化物材料是熱穩定和p 型或基於鉿的高電介質（HK）midgap 金屬的有效功函數（eWF）。不過，即使這些材料具有優異的熱穩定性。據報導，錫的HfSiON 閘極堆疊的MOSFET 有退化和載流子遷移率，當厚度的增加。為了提高穩定性和耐火金屬氮化物閘的電氣性能，我們已經提出了不同的方法。首先，將根據堆疊結構進行研究，如雙層結構，其中包括W / TiNx，和 Ta/ TaNx。此外，我們將修改在一個金屬氮的含量來調節有效功函數（eWF）。我們建議的工作是研究各種因子之優劣並最佳化金屬閘極（MG）與高電介質(HK) 並選定TiN 和TaN 作為金屬閘極，並瞭解物理和電氣性能經由TCAD 三維元件模擬軟體和製程相關的因子: TiN/TaN 厚度;TiN/TaN 的PVD 沉積直流電源強度;氮濃度;雙層式結構。相結合的辦法如下：第一部份 : 四種閘極結構將考慮於本研究中3D TCAD模擬 TiNx/HfSiO/Si TaNx/HfSiO/Si W/TiNx/HfSiO/SiO2/Si TaN/TaNx/HfSiO/SiO2/Si 第二部份 : 四種閘極結構將製程 TiNx/HfSiO/Si TaNx/HfSiO/Si W/TiNx/HfSiO/SiO2/Si TaN/TaNx/HfSiO/SiO2/Si 第三部份 : TiN 與 TaN 製程因子變數:(i) TiN/TaN 厚度影響: (10 nm; 30 nm; 50 nm) (ii) TiN /TaN PVD Deposition DC Power (1.5 kW; 2.5 kW; 5kW; 6 kW) (iii) 氮含量 (iv) 雙層式結構 Today advanced gate oxide stacks are evaluated for the future 28 nm and 10 nm nodes. Logic circuit technology is undergoing a materials revolution. Hafnium-based high-permittivity dielectrics have begun to replace the silicon oxide or silicon oxynitride gate insulator in metal-oxide-semiconductor field-effect transistors (MOSFETs), and metals are replacing the poly-crystalline (poly-Si) silicon gate electrode. As a result, metal gate (MG)/high-k dielectric (HK)/Si gate stacks have been heavily pursued. Metal nitrides are being considered as potential candidates for the mid-gap electrode due to their high thermal stability and compatibility with conventional CMOS processing. Employing metal gate electrodes in a conventional CMOS process poses new challenges. Metal nitride materials have been reported to be thermally stable and has a suitable effective work function (eWF) as a p-type or midgap metal on Hf-based high-k (HK) dielectrics. However, even though these materials have superior thermal stability. MOSFETs with a TiN/HfSiON gate stack reportedly experience degradation of carrier mobility and an increase in the electrical thickness. In order to improve the stabilities and electrical performance of the refractory metal nitride gates, we have proposed different methods. Firstly, the stacking structure will under be studied, such as dual-layer structure including W/TiNx, and Ta/TaNx. In addition, we will modify the nitrogen content in a metal to modulate the gate effective work function. In our proposed work, we will investigate various process options for optimizing the MG (metal gate) with HK (High-k) stack associated with TiN and TaN served as gate electrodes in studying the physical and electrical properties by 3D TCAD device simulation and process integration (TiN/TaN Thickness; TiN/TaN PVD Deposition DC Power; Nitrogen concentration; Dual-Layer). A combined approach as below: Part I: Four different MG/HK/Si gate stacking structures will need to be simulated by 3D TCAD: TiNx/HfSiO/Si TaNx/HfSiO/Si W/TiNx/HfSiO/SiO2/Si TaN/TaNx/HfSiO/SiO2/Si Part II: Four different MG/HK/Si gate stacking structures will need to be fabricated: TiNx/HfSiO/Si TaNx/HfSiO/Si W/TiNx/HfSiO/SiO2/Si TaN/TaNx/HfSiO/SiO2/Si Part III: TiN and TaN Metal Layer Process (i) Metal Thickness (10nm; 30 nm; 50 nm) (ii) TiN and TaN PVD Deposition Power (1.5kW;2.5kW;5 kW;6 kW)(iii) Nitrogen Content (iv) Dual-Layer The electrical characterization would offer explanations for the related experimental results and provide insight into the physical mechanism behind the formation of MG/HK/Si gate stack for sub-10 nm CMOS technology nodes. Indeed, it will all base on our experimental results.
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