本研究探討使用High-k and SiON材料為閘極絕緣體應用在低阻電源CMOS元件的瓶頸與限制,尤其以65/45奈米技術為主。一般而言，漏電流加大在奈米電晶體會造成direct tunneling的問題，這也是SiO2不能成為90以下奈米技術所採用。目前只有high-k材料是可以符合並且使用Poly-gate。但是high-k在poly gate是會產生channel mobility與reliability degradation以及Fermi level pinning的問題。因此SiON材料就會延續到65/45奈米技術。就最近的研究顯示SiON材料將是成功的取代材料，是在high-k材料沒有完成克服電子特性要求和VLSI製成技術成熟前的替代材料。
For low power applications, the increase of gate leakage current, caused by direct tunneling in ultrathin oxide films, is the crucial factor eliminating conventional SiO2-based gate dielectrics in sub-90nm CMOS technology development. Recently, promising performance has been demonstrated for poly-Si/High-k and poly-Si/SiON gate stacks in addressing gate leakage requirements for low power applications. However, the use of poly-Si gate electrodes on high-k created additional issues such as channel mobility and reliability degradations, as well as Fermi level pinning of the effective gate work function. Therefore, oxynitride gate dielectrics are being proposed as an intermediate solution toward the sub-65nm/45nm nodes. Apparently an enhanced SiON gate dielectric stack was developed and reported to achieve high dielectric constant and good interfacial properties. The purpose of this paper is to provide a comprehensive review some of the device performance and limitation that High-k and oxynitride as dielectric materials are facing for sub-65nm/45nm node.
