This work is mainly to study two different gate dielectric materials, SiO2 and Si3N4, for advanced CMOS applications. The design, simulation and analysis were based on different gate lengths comparing with these two materials and its device characteristic. As reducing the gate length toward to submicron CMOS device, selecting a gate dielectric material to improve the electric characteristics and been demonstrated by using ISE-TCAD simulation tool. As results, reducing the physical gate size and dielectric thickness, the device can sustain much less electric current. In additional, once leak electric current over the limit of bearing of the silicon, namely is Direct Tunneling. This is the reason that the SiO2 is not a good candidate for sub-90nm CMOS and below.
