先進加密標準(AES)矽智財之實現

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Please use this identifier to cite or link to this item: https://irlib.pccu.edu.tw/handle/987654321/22039

Title:	先進加密標準(AES)矽智財之實現
Other Titles:	The Silicon IP Implementation issue of Advanced Encryption Standard (AES)
Authors:	陳松彬廖偉廷李逸中劉宗慶
Contributors:	工學院
Date:	2006-06-01
Issue Date:	2012-04-18 14:54:21 (UTC+8)
Abstract:	我們根據美國國家標準局於2002年5月26日所發佈之Rijndael先進加密標準(AES)，針對該演算法分析與模擬後，再嘗試實體化。我們使用Modelsim發展Verilog RTL code，並用FPGA驗證，並探討速度最佳化。旨在設計一小硬體面積與高資料運算量之AES矽智財，即AES之硬體電路設計。在小硬體面積方面將從構成AES之關鍵要件S-box著手，本研究亦將嘗試設計一新電路架構以取代使用唯讀記憶體與隨機存取記憶體之方式以節省硬體耗用量。在高資料運算速度方面則使用管線化之硬體架構以縮短對資料作加密與解密的時間。最後則選用FPGA作為實現本設計之平台。 This paper deals with the algorithm analysis and implementation issue of the AES (Advanced Encryption Standard) used in the network security of modern communication systems, such as internet (intranet) and iTV systems. In detail, we use Matlab to simulate the Rijndael AES algorithm which has been selected to be the standard by NIST in the year 2002 among the five candidates and also perform the possible FPGA and hardware design analysis on implementation of a prototype AES chip.
Relation:	華岡工程學報 20期 p.49 -53
Appears in Collections:	[College of Engineering] Chinese Culture University Hwa Kang Journal of Engineering

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